1. Field of the Invention
The present invention relates to semiconductor memories such as large capacity dynamic random access memories (DRAMs). In particular, the invention relates to a semiconductor memory having a space-efficient layout by placing (master data line) MDQ switches into sense amplifier regions.
2. Description of Related Art
Large capacity memories typically contain sense amplifier banks between memory cell arrays. The sense amplifier banks occupy space on the surface of the chips. With demand for higher capacity memory chips, available surface area has become increasingly important to conserve and use as efficiently as possible. Memory chips are arranged in a plurality of rows and columns. A reduction in the size of a column, for example, could have a large impact on the size of the chip.
Referring to FIG. 1, a typical memory array 10 is shown. A sense amplifier bank 12 contains a plurality of sense amplifiers 14 for a column 16 of memory cells 18. Each column 16 of memory cells 18 includes a pair of complementary bit lines 20. During operation, a sense amplifier 14 "senses" a differential voltage between pair of complementary bit lines 20. During sensing the differential voltage, sense amplifier 14 amplifies the differential voltage to a bit line high voltage on one bit line of the pair and the other bit line is grounded. Either line can be driven high (bit line high) or low (ground) as required. This allows the memory cells in that column to store either a high or low bit as needed. A region 22 is shown containing three sense amplifiers 14 and a portion of a stitch-region 23, where no memory cells are located. Further in a segmented word line architecture, a local word line driver may be located in a corresponding free region.
Referring to FIG. 2, sense amplifier 14 usually contains large transistors used for driving the two separated halves of sense amplifier 14. The two halves of sense amplifier 14 include a P-amplifier 24 and an N-amplifier 26. Stitch-region 23 generally runs adjacent to columns 16, and stitch-region 23 has the same basic orientation as columns 16. Stitch-region 23 is an intermittent space, free of bit lines 20, hence creating space in which it is convenient to place necessary components. Regions for a multiplexing circuit containing isolation transistors are located in MUX regions 28 and 30. A bit line equalizer circuit containing equalization transistors are located in EQ regions 32 and 34. EQ regions 32 and 34 can be shared if one EQ is located between MUX regions 28 and 30. Both the MUX and EQ regions are allocated towards the ends of the sense amplifier bank 12 (FIG. 1).
P-amplifier 24 is located in the P-amplifier region 36 and N-amplifier 26 is located in the N-amplifier region 38. The transistors located in the stitch-region 23 include a PFET transistor (PFET) driver and an NFET transistor (NFET) driver 42. As mentioned, sense amplifier 14 includes an N-amplifier 38 and a P-amplifier 36. N-amplifier 38 is controlled by signal NFET driven by an NFET driver 42, and P-type amplifier 40 is controlled by signal PFET driven by a PFET driver 40. PFET 40 and NFET 42 drivers are usually used to drive a plurality of P-amplifiers or N-amplifiers as the case may be. PFET drivers 40 and NFET drivers 42 tend to be relatively large. A common placement location for PFET driver 40 and NFET driver 42 is within stitch-region 23 since there is space available for such placement. However, as demand increases this space becomes inadequate for placement of these devices. Further, PFET driver 40 requires placement over an N-well while NFET driver requires placement over a P-well. This further limits placement of PFET driver 40 to an area adjacent P-amplifier region 24 within stitch region 23 and NFET driver 42 adjacent to N-amplifier region 26, EQ regions 32 and 34 or MUX regions 28 and 30 within stitch region 23.
It is advantageous to be able to place a portion of PFET driver 40 and NFET driver 42 within regions 24 and 26, respectively, in order to better accommodate PFET driver 40 and NFET driver 42. Having drivers 40 and 42 within their respective amplifier regions will reduce RC time delays. However, such placement may cause bit lines to be rerouted due to contacts required to sources, gates and drains of PFET driver 40 and NFET driver 42.
Referring to FIG. 3, bit lines 20 are shown routed around contacts 46, 48 and 50. Contacts 46 and 50 extend downward to an active area AA through layer M0 which is the layer in which bit lines 20 are located. Metal lines 54 and 56 are used for connecting source 58 and drain 60 of NFET driver 42. N-amplifier 26 is shown schematically. Contact 48 of NFET driver 42 must also be avoided by bit lines 20. The rerouting of bit lines 20 reduces the available chip area reducing the space efficiency of the chip layout which is in direct conflict to the desire to reduce chip size.
Referring to FIG. 4, bit lines 20 are shown routed around contacts 46', 48' and 50'. Contacts 46' and 50' extend downward to an active area AA through layer M0 which is the layer in which bit lines 20 are located. Metal lines 54' and 56' are used for connecting source 58' and drain 60' of PFET driver 40'. P-amplifier 24 is shown schematically. Contact 48' of PFET driver 40 must also be avoided by bit lines 20. Again, the rerouting of bit lines 20 reduces the available chip area reducing the space efficiency of the chip layout which is in direct conflict to the desire to reduce chip size.
Space-efficient layouts have attempted to place devices such as master data line switches (MDQ switches) adjacent to sense amplifier bank to reduce overall chip layout area. MDQ switches are generally sparsely distributed across a chip. It is, therefore, desirable to place such devices in available free spaces to conserve layout area on a semiconductor memory chip.
Therefore, a need exists for placing MDQ switches within available space to create a more space-efficient layout without having to significantly reroute bit lines which could impact the overall size of the chip.